As shown in FIGS. 1 and 2 and as disclosed in U.S. Pat. No. 4,987,321, prior art correlated double sampling (CDS) circuits for image sensors 10 include capacitors 20 for storing charge from the image sensors 10 for subsequent measurement. In this regard, at time TA pulse SA turns on transistor 30a to charge capacitor 20a to voltage VA. At time TB, pulse SB turns on transistor 30b to charge to charge capacitor 20c to voltage VB. Capacitors 20a and 20c function to hold the sampled voltages VA and VB for the duration of one entire pixel period. At time TC, pulse SC turns on two transistors 30c and 30d to transfer the sampled voltages on capacitors 20a and 20c to capacitors 20b and 20d respectively. A differential amplifier 40 samples the voltages from the capacitors 20b and 20d for subtracting the two received voltages for ultimately determining the voltage for that particular pixel.
Although the currently known and utilized double sampling circuit is satisfactory, it includes drawbacks. The prior art CDS is capable of operation at only one pixel frequency. If the frequency is increased, the sampling pulses SA, SB and SC would be too short to fully charge the capacitors 20a through 20d. If the frequency is decreased, the CDS will function but the noise performance will remain the same as though the CDS is operated at its rated frequency.
Consequently, a need exists for a CDS that permits the CDS noise performance to be optimized for more than one frequency.